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Digital System Test and Testable Design: Using HDL Models and Architectures Zainalabedin Navabi Softcover Reprint of the Original 1st 2011 edition
Digital System Test and Testable Design: Using HDL Models and Architectures
Zainalabedin Navabi
This book is about digital system testing and testable design. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions.
435 pages, XVII, 435 p.
| Media | Books Paperback Book (Book with soft cover and glued back) |
| Released | August 23, 2016 |
| ISBN13 | 9781489979278 |
| Publishers | Springer-Verlag New York Inc. |
| Pages | 435 |
| Dimensions | 150 × 220 × 10 mm · 789 g |
| Language | English |
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