Logic Synthesis and SOC Prototyping: RTL Design using VHDL - Vaibbhav Taraate - Books - Springer Verlag, Singapore - 9789811513169 - January 30, 2021
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Logic Synthesis and SOC Prototyping: RTL Design using VHDL 2020 edition

Vaibbhav Taraate

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Logic Synthesis and SOC Prototyping: RTL Design using VHDL 2020 edition

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design.

251 pages, XIX, 251 p.

Media Books     Paperback Book   (Book with soft cover and glued back)
Released January 30, 2021
ISBN13 9789811513169
Publishers Springer Verlag, Singapore
Pages 251
Dimensions 500 g
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